Dynamic scheduling in the presence of faults: specification and verification
Janowski, T. and Joseph, M. (1996) Dynamic scheduling in the presence of faults: specification and verification. Technical Report. Department of Computer Science, Coventry, UK.
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A distributed real-time program is usually executed on a limited set of hardware resources and is required to satisfy timing constraints, despite anticipated hardware failures. Static analysis of the timing properties of such programs is often infeasible. This paper shows how to formally reason about these programs when scheduling decisions are made on-line and take into account deadlines, load and hardware failures. We use Timed CCS as a process description language, define a language to describe anticipated faults and apply a version of 5-calculus to specify and verify timing properties. This allows the property of schedulability to be the outcome of an equation-solving problem. And unlike conventional reasoning, the logic is fault-monotonic: if correctness is proved for a number of faults, correctness for any subset of these faults is guaranteed.
|Item Type:||Monograph (Technical Report)|
|Additional Information:||T. Janowski and M. Joseph, “Dynamic Scheduling in the Presence of Faults: Specification and Verification”, <i>Proceedings of the 4th FTRTFT Symposium</i>, Sweden, Lecture Notes in Computer Science 1135, Springer-Verlag, pp. 279-297 (1996)|
|Subjects:||Q Science > QA Mathematics > QA75 Electronic computers. Computer science|
|Divisions:||Faculty of Science > Computer Science|
|Depositing User:||Mr Ebrahim Ardeshir|
|Date Deposited:||22 Dec 2011 09:37|
|Last Modified:||01 Nov 2012 18:06|
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